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- Alam, Nazmul: Language Independent Modelling of Parallelism, Master Thesis No. 3554, 2014.
- Brösamle, Oliver: Manipulation der Typisierung serialisierter SKilL-Graphen, Master Thesis No. 17, 2018.
- Byanjankar, Prabin: Analysis of Effects of MISRA-Compliance on the Efficiency of Code Generated for ASCET Models, Master Thesis No. 1, 2009.
- Das, Rupak: Development of Differ and Merge Features for Models in the AMALTHEA Tool Platform, Master Thesis No. 95, 2016.
- Das, Sanjib: Analysis and Simulation of Scheduling Techniques for Real-Time Embedded Multi-core Architectures, Master Thesis No. 3578, 2014.
- Hafiz; Khan, Golam: Simulation of Multi-core Scheduling in Real-Time Embedded Systems, Master Thesis No. 3556, 2014.
- Hanna, Simon: Design und Implementierung eines Linkers für SKilL/Bauhaus, Master Thesis No. 39, 2018.
- Harrer, Matthias: Prototypenentwicklung mit Bauhaus und SKilL, Master Thesis No. 19, 2016.
- Jäger, Roland: Typesafe parallel serialization in SKilL/Rust, Master Thesis No. 42, 2018.
- Kayarat, Rekha: Advanced Multi-core Simulation of Real-Time Embedded Systems, Master Thesis No. 2015.
- Munk, Peter: Visualization of Scheduling in Real-Time Embedded Systems, Master Thesis No. 3372, 2013.
- Pfister, Daniel: Skilled LLVM, Master Thesis No. 67, 2018.
- Przytarski, Dennis: SKilLed Bauhaus, Master Thesis No. 35, 2016.
- Quack, Daniel: Data Race Analyse in SKilL/Bauhaus, Master Thesis No. 69, 2018.
- Roth, Jonathan: Reduktion des Speicherverbrauchs generierter SKilL-Zustände, Master Thesis No. 19, 2015.
- Schnaible, Sven: Modelle und Programmierparadigmen für Geschäftslogik, Master Thesis No. 79, 2016.
- Sheshadri, Vinay: MatLab/Simulink model generation from a database, Master Thesis No. 120, 2017.
- Weißer, Constantin Michael: Serialization of Foreign Types with SKilL, Master Thesis No. 2016.
- Zhang, Zao: Increasing the Simulation Speed of a Virtual Prototype of an SDR Baseband Platform by Parallelization, Master Thesis No. 16, 2005.
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